News & Events
CCCD Workshop 2007
of Success in Wireless SoC - A Solid Foundation for the Future"
September 6-7, 2007
Grand Hotel, Lund
The Competence Center for Circuit Design (CCCD) was formally established on
January 1, 1998, at the Department of Applied Electronics (now Electroscience),
Lund University, along with VINNOVA and a number of industrial partners.
With the focus set on mobile communication and strategic goal of system-on-chip,
all aspects in circuit design from monolithic radio front-end through analog
mixed-signal ASIC to digital and DSP-ASIC are well represented in the center.
Analog and RF Design
Analog and RF Circuit Design will always face challenges in the form of
shrinking design boundaries, higher performance require-ments, and the
need for fully integrated solutions. Demands are increasing due to the
evolution of process technology, which enables higher frequencies but at
the same time lowers the limits for supply voltage, which in turn lessens
voltage headroom and dynamic range.
As technology improves, new circuit architecture must be developed and
older building blocks must be re-examined to ensure that they meet the new
standards of wireless communica-tion. It is likely that, within a few
years, MOS transistors will operate in weak inversion. This change in the
analog design space will create further challenges. And since many of the
new applications assume very low-cost implementations of high frequency
building blocks, low-cost technology such as main-stream CMOS will become
To address these demands, the Analog and RF Circuit Design Group is
currently running several projects that consider design issues ranging
from the architectural level to crucial building blocks.
This group is divided into two sub-areas: Monolithic Transceivers and
Linearization Techniques; and includes Associate Professor Henrik Sjöland,
Adjunct Professors Sven Mattisson and Lars Sundström, and ten Ph.D.
Mixed Signal Design
The group's research has been focused on three areas of mixed signal IC
design for wireless communication systems. The first and second concern
the bottlenecks of a heterogeneous system, i.e. high performance A/D and
D/A conversions with an emphasis on speed, accuracy, dynamic range, low
power, low voltage and embedded solutions. The third concerns one of the
key issues for system-on-chip integration, i.e. the design methodology for
reducing the interference between different parts of a hetero-geneous
system, such as low noise emitting digital circuit techniques and robust
analog circuit solutions.
The research topics of the Mixed Signal Circuit Design Group include: Wide
Dynamic Range A/D Converters, Low-Glitch and RF D/A Converters, High Speed
Early Sampling and Digitizing, and Design Techniques for Single Chip Mixed
Signal Circuits and Systems. Circuit implementations include
floating-point ADC, interpolation DAC, direct digital RF quadrature
modulator, charge-sampling ADC and FIR filter, interpolation multi-phase
clock generators, and silent digital logic circuits, etc. To date, the
Mixed Signal Design group has transferred three patents to its industrial
partners in these areas.
This group includes Professor Jiren Yuan and six Ph.D. students.
Digital ASIC Design
During the 90's, functionality of digital integrated circuits in-creased
considerably. At the same time, due to the increasing complexity of
systems, the complexity of the algorithms neces-sary to implement on a
single die also increased. Moore's law is not sufficient to sustain these
increasing demands in complexity, and hardware efficient implementation
and increased integration are essential to achieving competitive
Unfortunately, EDA-tools and design methodologies have not pro-gressed at
the same rate, which has left a design gap between the number of
transistors that can be implemented on a single die and the number that
can be used efficiently.
New strategies that balance the conflicting requirements of
calculation capacity, power consumption, flexibility, and (to some extent)
silicon area are needed to bridge this gap. MIPS-intensive parts are the
most power hungry and should be considered for application specific
implementation. By utilizing tailored archi-tectures and streamlined
dataflow, several orders of magnitude of improvement in power savings
and/or calculation capacity can be gained.
The research within the Digital ASIC group explores new metho-dologies and
new architectures in an effort to create efficient solutions that take
into account all levels of circuit design, including the development of
hardware accelerators as a comple-ment to programmable kernels. By
collaborating with theoretical researchers to explore the field of
algorithm/hardware co-opti-mization, we can find algorithmic trade-offs
between perform-ance and implementation complexity. Furthermore, key
building blocks of digital circuits are implemented for use in other
projects. Generic design techniques like arithmetic explorations and
on-chip clocking strategies are also investigated.
This group includes Associate Professors Peter Nilsson and Viktor Öwall,
Adjunct Professor Mats Torkelson, and thirteen Ph.D. students.